Research
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Bent-Pyramid: Towards A Quasi-Stochastic Data Representation for AI Hardware
Abstract
The applications of the Artificial Intelligence have been increasingly used with huge datasets for many purposes. The beyond Von Neumann architectures (like digital and analog in-memory computing) are proposed to mitigate the data-movem...
Publication · June 10, 2025
Digital in-memory stochastic computing architecture for vector-matrix multiplication
Abstract
The applications of the Artificial Intelligence are currently dominating the technology landscape. Meanwhile, the conventional Von Neumann architectures are struggling with the data-movement bottleneck to meet the ever-increasing perfor...
Publication · June 10, 2025
CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA
Abstract
This letter presents CIFER, the world’s first open-source, fully cache-coherent, heterogeneous many-core, CPU-FPGA system-on-chips. The 12 nm, 16-mm2 chip integrates four 64-bit, OS-capable, RISC-V application cores; three TinyCore clus...
Publication · June 10, 2025
A 1T1R+2T Analog Content-Addressable Memory Pixel for Online Template Matching
Abstract
The template matching approach has a promising momentum to build energy-efficient edge classifiers for var-ious implantable and wearable medical devices. To mitigate the analog/digital cross-domain interfacing complexity, analog content...
Publication · June 10, 2025
PyT-NeuroPack: A Hybrid PyTorch/Memristor-Crossbar Simulation Tool for Convolutional Neural Networks
Abstract
In-Memory Computing (IMC) is gaining attention to deploy large-scale architectures for AI-oriented vector-matrix multiplications. Memristor-crossbars encapsulate these features performing computations using Ohm's and Kirchhoff's current...
Publication · June 10, 2025
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Dataflow and Analytical Modelling
Abstract
In order to follow the ever-growing computational complexity and data intensity of state-of-the-art AI models, new computing paradigms are being proposed. These paradigms aim at achieving high energy efficiency, by mitigating the Von Ne...
Publication · June 10, 2025
A 9T4R RRAM-Based ACAM for Analogue Template Matching at the Edge
Abstract
The continuous shift of computational bottlenecks to the memory access and data transfer, especially for AI applications, poses the urgent needs of re-engineering the computer architecture fundamentals. Many edge computing applications,...
Publication · June 10, 2025
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation
Abstract
Modern hardware architectures for Convolutional Neural Networks (CNNs), other than targeting high performance, aim at dissipating limited energy. Reducing the data movement cost between the computing cores and the memory is a way to mit...
Publication · June 10, 2025
DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration
Abstract
Transformers are gaining increasing attention across different application domains due to their outstanding accuracy. However, these data-intensive models add significant performance demands to the existing computing architectures. Syst...
Publication · June 10, 2025
An Energy-Efficient Capacitive-RRAM Content Addressable Memory
Abstract
Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density and a decrease in power consumption than pure CMOS solu...
Publication · June 10, 2025
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